1. Field of the Invention
The invention generally relates to an image display technique. More particularly, the invention relates to an addressing technique for setting the addresses of a plurality of driving chips in an image display system.
2. Description of Related Art
As development of image displays trend towards larger device dimensions, a display such as a large television panel usually form images from a plurality of blocks. In order to provide local dimming for the blocks, an entire display panel is divided into multiple blocks, for example 16×8 blocks. An external control unit can independently control the brightness of the blocks. FIG. 1 is a schematic diagram illustrating a display system driven by dividing the display system into a plurality of blocks. Referring to FIG. 1, a display panel 100 of the display system can be divided into nine blocks 102 numbered 1-9, in which a system unit 108 controls nine driving chips 104 in a driving unit 106 corresponding to each of the blocks 102 for respectively controlling the brightness of the display panel 100, for example.
The system unit 108 usually transmits commands to the driving unit 106 through a serial interface. According to the commands received, the driving unit 106 adjusts a local brightness of the blocks in order to satisfy the requirements for a high performance of image display such as high contrast ratio and high gray level. According to an address transmitted by the external system unit 108, the driving chip 104 disposed in each of the blocks determine whether or not to allow reception of data corresponding to the driving chip 104, and thereafter enable a mechanism for brightness adjustment. In other design mechanisms, the driving chip 104 can determine whether or not to receive data based on the validity of the time slot corresponding to the driving chip.
Consequently, each driving chip needs to be set with an address by hardware. In one conventional technique, pin settings of the driving chip are externally determined. With different sets of blocks such as 16×8, 7 extra corresponding pins are needed. FIG. 2 is a schematic diagram illustrating a circuit structure using a conventional pin setting mechanism. Referring to FIG. 2, each of the driving chips 104 is respectively connected with the system 108 and respectively set with pin addresses Addr—0-Addr_n, so that all driving chips 104 have their corresponding addresses.
In another conventional technique where external pin settings are also utilized, an internal ADC is used to detect an external input voltage for determining the addresses of the driving chips. However, in practical applications the decision making can be easily affected by signal interference. Moreover, combination of the two aforementioned techniques can increase complexity in hardware design. Another conventional technique involves address setting the driving chips before dispatch from the factories, although this can increase the complexity of inventory management.
Another conventional technique involves the aforementioned time slot method, in which data is allowed to be received when the corresponding time slot for the driving chip is matched. FIG. 3 is a schematic diagram illustrating a circuit design in accordance with a conventional time slot receiving mechanism. Referring to FIG. 3, a data output terminal DATO of a previous-stage driving chip 110 is connected by a path 112 to an input terminal DATI of a next-stage driving chip 110, so that data is transmitted to all of the driving chips 110 in sequence. In this technique, not only is a clock terminal Clk needed for inputting a clock, if a particular data needs to be modified, for example within a block, then data in all of the blocks needs to be retransmitted. Since transmission failures in any path also result in retransmissions, there are significant time costs involved with this technique.
Therefore, the conventional chip addressing method and structure can be further developed.